EXPANDING THE CCX WITH ZEN 3

Zen and Zen 2 were designed around a module known as a CPU/Core Complex (or CCX) which featured four CPU cores, each with private L1 and L2 cache, and a shared pool of L3 cache. Up to two CCX’s would be active on a single processor die, and data in one CCX L3 cache pool could be accessed by the other CCX across the ‘infinity fabric’ pathways at speeds tied to memory clocks.

Cross-CCX cache querying, and the latency it introduced, was one of the highlighted weaknesses of Zen modular design. It was partially mitigated by the massively increased L3 cache present in Zen 2’s chiplet implementation (which was primarily intended to mitigate against increased memory latency), but that was sidestepping the problem somewhat.

Zen 3 redesigns the CCX by expanding up to 8 cores, each with the same allocation of L1 and L2 cache, and allowing all 32MB L3 Cache to be shared by the cores at the same latency. Hopping between CCX’s now need only occur when hopping between CCD’s, a factor that’s also irrelevant for the 6- and 8-core 5600X and 5800X.

This is far from the only change introduced with the Zen 3 architecture - AMD are keen to emphasise that gaining large IPC margins requires heavy revision from the front to the back of the CPU - but it’s the most stark.

BROAD ARCHITECTURAL IMPROVEMENTS

AMD claim an averaged 19% IPC uplift with Zen 3 compared to Zen 2, but no single development led to this improvement. Instead, a combination of aspects of the Zen processing pipeline have been overhauled to push the CPU this far, each contributing in significant ways.

These improvements are highly technical but can be placed under three broad banners:





Zen 3 began with the goal of delivering performance leadership across all aspects of desktop computing. Multi-core performance was already licked thanks to the strong SMT implementation and a 16-core flagship SKU, but Zen 2 still trailed in lightly threaded tasks that relied on IPC and raw clock speed, particularly gaming.

So it's telling that although that 19% headline improvement to IPC is impressive by itself, many of the gains are concentrated in gaming workloads particularly. In this subset of workloads the benefits could be as high as 39% at appropriate rendering resolutions, resolutions that tax the CPU without bottlenecking on the GPU (typically 1080p).



Preliminary testing also indicates that Zen 3 gains further from a faster (i.e. RTX 30-series) GPU than its competition, but the selection of results available with this relatively new system configuration is limited at this time.

MEMORY CONTROLLER

The Ryzen 5000-series IO Die (IOD) is identical to the IOD of the 3000-series, and so the general principles learned remain unchanged. DDR4 3200 is still the recommended memory to pair with the processors prior to entering an overclocked state, and the default relationships between DRAM Memory (memclk), Unified Memory Controller (UMC) and Infinity Fabric (fclk) clocks still operates in a 1:1:1 ratio.

The maximum memory capacity is 128GB DDR4 (4x32GB), and EEC memory is supported but remains unqualified on the mainstream platform. EEC support will therefore vary on a motherboard by motherboard basis.



Under overclocked conditions the memory clock can be increased in 33MHz increments beyond the spec of the memory controller, with memclk and UMC remaining in lockstep. It is possible however to shift the fclk ratio to 1:2, stepping it down to half the UMC clock and thereby potentially increasing system stability at higher memclk/UMC. Optimum operation is typically when in a 1:1:1 ratio however.

The Ryzen 3000-series was generally understood to hit a memory overclocking sweet spot of ~3800MHz DDR4, after which the infinity fabric ratio would need to be stepped down. AMD project that the equivalent 5000-series sweet-spot is ~4000MHz, no-doubt pleasing memory manufacturers the world over. Achieving this isn’t guaranteed, and may require the latest launch BIOSes on 500-series motherboards.